TMDS171 datasheet(6/63 Pages) TI2

6 / 63 page

TMDS171, TMDS171I

SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017

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Pin Functions (continued)

I/O(1)

DESCRIPTION

NAME

NO.

High address bit 2 for I2C programming

Weak internal pull down.

Note: When I2C_EN/PIN = Low for Pin Strapping Mode leave this pin as No connect

TX_TERM_CTL

3-Level

Transmit Termination Control

TX_TERM_CTL = H: No transmit Termination

TX_TERM_CTL = L: Reserved

TX_TERM_CTL = No Connect: Automatically selects the termination impedance

2 Gbps > DR

≤ 3.4 Gbps – 150 - 300 Ω differential near end termination

DR < 2 Gbps – no termination

Note: If left floating; the device will be in Automatic Select Mode. DR stands for Data Rate

SWAP/POL

3-Level

Receive Polarity Swap and Receive Lane Swap control pin

SWAP/POL = H: Receive Lanes Polarity Swap (Retimer Mode Only)

SWAP/POL = L: Receive Lanes (Retimer and Redriver Mode)

Swap SWAP/POL = No Connect, Normal Operation

18, 40

–

No connect

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential voltages, are with respect to network ground terminal.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-B

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

MIN

MAX

UNIT

Supply Voltage Range

VCC

–0.3

VDD

–0.3

1.4

Voltage Range

Main Link Input Differential Voltage (IN_Dx,

IN_CLKx); IIN = 15mA

VCC - 0.75 V

VCC + 0.3 V

TMDS Outpus ( OUT_Dx)

–0.3

HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1,

PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN,

TX_TERM_CTL,

–0.3

HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC,

SCL_SRC

–0.3

Input Current IIN

Main Link Input Differential Voltage (IN_Dx,

IN_CLKx);

Continuous power dissipation

See Thermal Information

Storage temperature, Tstg

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2)

±500

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