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TMDS171 Datasheet(PDF) 11 Page - Texas Instruments |
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TMDS171 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 63 page ![]() 11 TMDS171, TMDS171I www.ti.com SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017 Product Folder Links: TMDS171 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Switching Characteristics (continued) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD (2) Cb = total capacitance of one bus line in pF. tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6 0.15 Tbit tJITC2 Total output clock jitter CLK Rate ≤ 340 MHz 0.25 Tbit tJITD2 Total output data jitter DR ≤ 3.4 Gbps; See Figure 11 0.2 Tbit HPD tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge(1) see Figure 13; not valid during switching time 40 120 ns tT(HPD) HPD logical disconnected timeout see Figure 14 2 ms DDC and I2C tr Rise time of both SDA and SCL signals VCC = 3.3 V 300 ns tf Fall time of both SDA and SCL signals 300 tHIGH Pulse duration, SCL high 0.6 µs tLOW Pulse duration, SCL low 1.3 tSU1 Setup time, SDA to SCL 100 ns tST,STA Setup time, SCL to start condition 0.6 µs tHD,STA Hold time, start condition to SCL 0.6 tST,STO Setup time, SCL to stop condition 0.6 t(BUF) Bus free time between stop and start condition 1.3 tPLH1 Propagation delay time, low-to-high- level output Source to Sink:100 kbps pattern; Cb(Sink) = 400 pF (2); see Figure 17 360 ns tPHL1 Propagation delay time, high-to-low- level output 230 tPLH2 Propagation delay time, low-to-high- level output Sink to Source: 100 kbps pattern; Cb(Source) = 100 pF (2); see Figure 18 250 tPHL2 Propagation delay time, high-to-low- level output 200 |
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