Electronic Components Datasheet Search
  English  ▼

X  

TMDS171 Datasheet(PDF) 11 Page - Texas Instruments

Part # TMDS171
Description  TMDS171/I 3.4 Gbps TMDS RETIMER
PDF  63 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TMDS171 Datasheet(HTML) 11 Page - Texas Instruments

Back Button TMDS171 Datasheet HTML 7Page - Texas Instruments TMDS171 Datasheet HTML 8Page - Texas Instruments TMDS171 Datasheet HTML 9Page - Texas Instruments TMDS171 Datasheet HTML 10Page - Texas Instruments TMDS171 Datasheet HTML 11Page - Texas Instruments TMDS171 Datasheet HTML 12Page - Texas Instruments TMDS171 Datasheet HTML 13Page - Texas Instruments TMDS171 Datasheet HTML 14Page - Texas Instruments TMDS171 Datasheet HTML 15Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 63 page
background image
11
TMDS171, TMDS171I
www.ti.com
SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017
Product Folder Links: TMDS171
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
Switching Characteristics (continued)
The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at
3.3 V VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD
(2)
Cb = total capacitance of one bus line in pF.
tSK_INTRA
Intra-pair output skew
Default setting for internal intra-pair
skew adjust, PRE_SEL = NC;
TX_TERM_CTL = NC, DR
≤ 3.4
Gbps; See Figure 6
0.15
Tbit
tJITC2
Total output clock jitter
CLK Rate
≤ 340 MHz
0.25
Tbit
tJITD2
Total output data jitter
DR
≤ 3.4 Gbps; See Figure 11
0.2
Tbit
HPD
tPD(HPD)
Propagation delay from HPD_SNK
to HPD_SRC; rising edge and falling
edge(1)
see Figure 13; not valid during
switching time
40
120
ns
tT(HPD)
HPD logical disconnected timeout
see Figure 14
2
ms
DDC and I2C
tr
Rise time of both SDA and SCL
signals
VCC = 3.3 V
300
ns
tf
Fall time of both SDA and SCL
signals
300
tHIGH
Pulse duration, SCL high
0.6
µs
tLOW
Pulse duration, SCL low
1.3
tSU1
Setup time, SDA to SCL
100
ns
tST,STA
Setup time, SCL to start condition
0.6
µs
tHD,STA
Hold time, start condition to SCL
0.6
tST,STO
Setup time, SCL to stop condition
0.6
t(BUF)
Bus free time between stop and start
condition
1.3
tPLH1
Propagation delay time, low-to-high-
level output
Source to Sink:100 kbps pattern;
Cb(Sink) = 400 pF
(2); see Figure 17
360
ns
tPHL1
Propagation delay time, high-to-low-
level output
230
tPLH2
Propagation delay time, low-to-high-
level output
Sink to Source: 100 kbps pattern;
Cb(Source) = 100 pF
(2); see Figure 18
250
tPHL2
Propagation delay time, high-to-low-
level output
200



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com