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TMDS171 Datasheet(PDF) 28 Page - Texas Instruments

Part # TMDS171
Description  TMDS171/I 3.4 Gbps TMDS RETIMER
PDF  63 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TMDS171 Datasheet(HTML) 28 Page - Texas Instruments

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VOD(SS) = 1020mVpp
VOD(PP) = 1200mVpp
1
st bit
2
nd to N bit
PRE_SEL = Z
Vsadj = 7.06<Q
Vsadj = 7.06<Q
I2C Reg0Ch[7:5] = 011
Reg0C[1:0] = 01
28
TMDS171, TMDS171I
SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017
www.ti.com
Product Folder Links: TMDS171
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
Figure 29. Pre-emphasis Using I2C
8.4 Device Functional Modes
8.4.1 Retimer Mode
Clock and Data Recovery Circuits (CDR) are used to track, sample and retime the equalized data bit streams.
The CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to
the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz, is transferred to the TMDS outputs.
Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce
the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock
above approximately 100 MHz when jitter cleaning is needed for robust operation. The retimer operates at about
100 Mhz – 340 MHz pixel clock (1 – 3.4 Gbps). At pixel clock below about 100 MHz, the TMDS171 automatically
bypasses the internal retimer, and operates as a redriver. When the video source changes resolution, the internal
retimer starts the acquisition process to determine the input clock frequency and acquire lock to the new data bit
streams. During the clock frequency detection period and the retimer acquisition period that last approximately 7
ms, the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or
data to the downstream receiver. The TMDS171 can support retimer mode across the full data rate range of 250
Mbps - 3.4 Gbps by setting DEV_FUNC_MODE bits at reg0Ah[1:0], See Table 9. For compliance testing such as
JTOL for 480 Mbps the PLL must be forced to lock.
8.4.2 Redriver Mode
The TMDS171 can function as a redriver which compensates for ISI channel loss. In this mode, power is
reduced as the CDR and PLL are turned off. When in automatic mode, the TMDS171 is in redriver mode for data
rates < 1.0 Gbps. By using I2C the device can be put in Redriver mode for the complete data range of 250 Mbps
to 3.4 Gbps. This is done by writing a 00 to register 0Ah[1:0]. If the link has excessive random jitter then retimer
mode is the best operating mode. If the link has excessive random jitter, the retimer mode is the best operating
mode. When in redriver mode, the device compensates for ISI loss only. When in redriver mode compliance is
not ensured as skew compensation and retiming functions are disabled. If a significant amount of random jitter is
present, the system may not pass compliance at the connector.



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