TMDS171 datasheet(46/63 Pages) TI2

46 / 63 page

TMDS171, TMDS171I

SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017

www.ti.com

Product Folder Links: TMDS171

Submit Documentation Feedback

Source Side Application (continued)

9.2.1 Design Requirements

The TMDS171 can be designed into many different applications. In all the applications there are certain

requirements for the system to work properly. Two voltage rails are required in order to support lowest power

consumption possible. OE pin must have a 200 nF capacitor to ground. This pin can be driven by a processor

but the pin needs to change states after voltage rails have stabilized. The best way to configure the device is by

using I2C but pin strapping is also provided as I2C is not available in all cases. As sources may have many

different naming conventions it is necessary to confirm that the link between the source and the TMDS171 are

correctly mapped. A Swap function is provide for the input pins incase signaling if reversed between source and

device. Table 34 provides information on expected values in order to perform properly.

Table 34. Design Parameters

PARAMETER

VALUE

VCC

3.3 V

VDD

1.2 V

Main Link Input Voltage

VID = 75 mVPP to 1.4 VPP

Control Pin Max Voltage for Low

65 kΩ pulldown

Control Pin Voltage Range Mid

Left Not Connected/Floating

Control Pin Min Voltage for High

65 kΩ pullup

R(VSADJ) Resistor

7.06 kΩ 1%

9.2.2 Detailed Design Procedure

The TMDS171 is a signal conditioning device that provides several forms of signal conditioning in order to

support compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished

using receive equalization, retiming, and output driver configurability. The transmitter will drive 2-3” of board trace

and connector when compliance is required at the connector.

To design in the TMDS171 the following need to be understood for a source side application:

•

Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.

•

Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass

source electrical compliance. Usually within 2”-3” of the connector

•

Use the typical application Figure 57 for information on control pin resistors.

•

The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.

•

Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support compliance by using

the appropriate VSADJ resistor value and setting PRE_SEL, and TX_TERM_CTL control pins.

•

The thermal pad must be connected to ground.

•

See Figure 57 for recommended decouple capacitors from VCC and VDD pins to Ground

9.2.3 Application Curves

Figure 58. 1080p Compliance Eye

Figure 59. 4k2k30 Compliance Eye

TMDS171 Datasheet(PDF) 46 Page - Texas Instruments

TMDS171 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL