TMDS171 datasheet(8/63 Pages) TI2

8 / 63 page

TMDS171, TMDS171I

SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017

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(1)

ICC is a direct result of the source design as the TMDS171 integrated receive termination resistor accounts for 85 mA to 100 mA.

(2)

IDD is impacted by ARC usage. Connecting a 500 KΩ resistor to GND at SPDIF reduces the value by more than 20 mA.

(3)

The measurements were made with no active source connected.

6.5 Electrical Characteristics

The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at

3.3 VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply

P(D1)

(1) (2)

Device power Dissipation

(Retimer Operation)

OE = H, VCC = 3.3 V / 3.465 V, VDD = 1.2 V / 1.27 V

IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL= H,

EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V

3.4 Gbps TMDS pattern, VI = 3.3 V; VSADJ = 7.06 kΩ

675

875

P(D2)

(1) (2)

Device power Dissipation

(Redriver Operation)

400

600

P(SD1)

(1) (2) (3)

Device power in Standby

OE = H, VCC = 3.3 V / 3.465 V

VDD = 1.2 V / 1.27 V , HPD = H,

No Valid input Signal

100

P(SD2)

(1) (2) (3)

Device power in PowerDown

OE = L, VCC = 3.3 V / 3.465 V

VDD = 1.2 V / 1.27 V

ICC1

(1) (2)

VCC Supply current (TMDS 3.4

Gpbs Retimer Mode)

OE = H, VCC = 3.3 V / 3.465 V

VDD = 1.2 V / 1.27 V

IN_Dx: VID_PP = 1200 mV,

3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,

EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

140

IDD1

(1) (2)

VDD Supply current (TMDS 3.4

Gpbs Retimer Mode)

286

325

ICC2

(1) (2)

VCC Supply current (TMDS 3.4

Gpbs Redriver Mode)

OE = H, VCC = 3.3 V / 3.465 V

VDD = 1.2 V / 1.27 V

IN_Dx: VID_PP = 1200 mV,

3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,

EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H

IDD2

(1) (2)

VDD Supply current (TMDS 3.4

Gpbs Redriver Mode)

188

I(SD1)

(3)

Standby current

OE = H, VCC = 3.3 V / 3.465 V

VDD = 1.2 V / 1.27 V

HPD = H: No valid signal on

IN_CLK

3.3V Rail(1)

1.2V Rail

I(SD2)

(3)

PowerDown current

OE = L, VCC = 3.3 V / 3.465 V

VDD = 1.2 V / 1.27 V

3.3V Rail(1)

1.2V Rail

3.5

TMDS Differential Input

D(R_RX_DATA)

TMDS data lanes data rate

0.25

3.4

Gbps

D(R_RX_CLK)

TMDS clock lanes clock rate

340

MHz

tRX_DUTY

Input clock duty circle

40%

50%

60%

tCLK_JIT

Input clock jitter tolerance

0.3

Tbit

tDATA_JIT

Input data jitter tolerance

Test the TTP2 See Figure 11

150

tRX_INTRA

Input intra-pair skew tolerance

Test at TTP2 when DR = 1.6 Gbps See Figure 11

112

tRX_INTER

Input inter-pair skew tolerance

1.8

EQH(D)

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps

EQL(D)

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps

7.5

EQZ(D)

Adaptive EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0=NC; adaptive EQ

EQ(C)

EQ gain for clock lane

IN_CLKn/p

EQ_SEL/A0=H,LNC

R(INT)

Input differential termination

impedance

100

115

TMDS Differential Output

VOH

Single-ended high level output

voltage

PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750

Mbps; VSadj = 7.06 kΩ

VCC -

10mV

VCC +

10mV

PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97

Gbps; VSadj = 7.06 kΩ

VCC -

200mV

VCC +

10mV

VOL

Single-ended low level output

voltage No Pre-emphasis,

Load is 50 Ω pull ups to 3.135

V and 3.465 V

PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750

Mbps; VSadj = 7.06 kΩ

VCC -

600mV

VCC -

400mV

PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97

Gbps; VSadj = 7.06 kΩ

VCC -

700mV

VCC -

400mV

TMDS171 Datasheet(PDF) 8 Page - Texas Instruments

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