TMDS171 datasheet(34/63 Pages) TI2

34 / 63 page

TMDS171, TMDS171I

SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017

www.ti.com

Product Folder Links: TMDS171

Submit Documentation Feedback

8.5.6 CSR BIT Field Definitions – Misc Control (offset: 00001011) (reset: 00h)

Figure 34. CSR Bit Field Definitions – Misc Control (0Bh)

R/W/U

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 10. CSR Bit Field Definitions – Misc Control (0Bh)

Bit

Field

Type

Reset

Description

7:5

Reserved

2’b000

Reserved

4:3

TX_TERM_CTL

RWU

2’b00

Controls termination for HDMI TX; Writes are ignored when

I2C_EN/PIN = 0

00 – No termination

01 – 150 to 300 Ω

10 – Reserved.

11 – Reserved

DDC_DR_SEL

R/W

1’b0

Defines the DDC output speed for both DDC bridge and AUX-

DDC Bridge.

0 = 100 kbps (default)

1 = 400 kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be

set before enabling 400 Kbps mode)

1:0

Reserved

2’b00

Reserved

TMDS171 Datasheet(PDF) 34 Page - Texas Instruments

TMDS171 Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL