TMDS171 datasheet(5/63 Pages) TI2

5 / 63 page

TMDS171, TMDS171I

www.ti.com

SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017

Product Folder Links: TMDS171

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(1)

(1) G = Ground, I = Input, O = Output, P = Power

(2)

(H) Logic High (Pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (Pin strapped to GND through 65 kΩ resistor); (Mid-Level =

No connect)

Pin Functions

I/O(1)

DESCRIPTION

NAME

NO.

VCC

13, 43

3.3 V Power Supply

VDD

14, 23, 24, 37, 48

1.2 V Power Supply

GND

7, 19, 41, 30

Ground

Thermal Pad

Ground

MAIN LINK INPUT PINS (FAIL SAFE)

IN_D2p/n

2, 3

Channel 2 Differential Input

IN_D1p/n

5, 6

Channel 1 Differential Input

IN_D0p/n

8, 9

Channel 0 Differential Input

IN_CLKp/n

11, 12

Clock Differential Input

MAIN LINK OUTPUT PINS (FAIL SAFE)

OUT_D2n/p

34, 35

TMDS Data 2 Differential Output

OUT_D1n/p

31, 32

TMDS Data 1 Differential Output

OUT_D0n/p

28, 29

TMDS Data 0 Differential Output

OUT_CLKn/p

25, 26

TMDS Clock Differential Output

HOT PLUG DETECT PINS

HPD_SRC

Hot Plug Detect Output to source side

HPD_SNK

Hot Plug Detect Input from sink side

AUDIO RETURN CHANNEL and DDC PINS

SPDIF_IN

SPDIF signal input

ARC_OUT

Audio return channel output

SDA_SRC

I/O

Source Side TMDS Port Bidirectional DDC Data line

SCL_SRC

I/O

Source Side TMDS Port Bidirectional DDC Clock line

SDA_SNK,

I/O

Sink Side TMDS Port Bidirectional DDC Data Line

SCL_SNK

I/O

Sink Side TMDS Port Bidirectional DDC Clock Line

CONTROL PINS(2)

Operation Enable/Reset Pin

OE = L: Power Down Mode

OE = H: Normal Operation

Internal weak pull up: Resets device when transitions from H to L

SIG_EN

Signal detector circuit enable

SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default)

SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby

Mode.

Internal weak pull down

PRE_SEL

3-Level

De-emphasis Control when I2C_EN/PIN = Low.

PRE_SEL = L: -2 dB

PRE_SEL = No Connect: 0 dB

PRE_SEL = H: Reserved

When I2C_EN/PIN = High; De-emphasis is controlled through I2C

EQ_SEL/A0

Input Receive Equalization pin strap when I2C_EN/PIN = Low

EQ_SEL = L: Fixed EQ at 7.5 dB

EQ_SEL = No Connect: Adaptive EQ

EQ_SEL = H: Fixed at 14 dB

When I2C_EN/PIN = High Address Bit 1

Note: 3 level for pin strap programming but 2 level when I2C address

I2C_EN/PIN

I2C_EN/PIN = High; Puts Device into I2C Control Mode

I2C_EN/PIN = Low; Puts Device into Pin Strap Mode

SCL_CTL

I/O

I2C Clock Signal when I2C_EN/PIN = High.

Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be

changed by I2C

SDA_CTL

I/O

I2C Data Signal when I2C_EN/PIN = High

Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be

changed by I2C

VSadj

TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND

TMDS171 Datasheet(PDF) 5 Page - Texas Instruments

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