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TMDS171 Datasheet(PDF) 41 Page - Texas Instruments

Part # TMDS171
Description  TMDS171/I 3.4 Gbps TMDS RETIMER
PDF  63 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TMDS171 Datasheet(HTML) 41 Page - Texas Instruments

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TMDS171, TMDS171I
www.ti.com
SLLSEN7E – OCTOBER 2015 – REVISED SEPTEMBER 2017
Product Folder Links: TMDS171
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
8.5.24 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)
Figure 52. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 28. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
4’b0000
Reserved
3:0
BERT_CNT[35:32]
R/U
4’b0000
BERT error count. Lane 2
8.5.25 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)
Figure 53. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/U
R/U
R/U
R/U
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 29. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)
Bit
Field
Type
Reset
Description
7:0
BERT_CNT[19:12]
R/U
’h00
BERT error count. Lane 3
8.5.26 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)
Figure 54. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R/U
R/U
R/U
R/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 30. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
4’b0000
Reserved
3:0
BERT_CNT[23:20]
R/U
4’b0000
BERT error count. Lane 3
8.5.27 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)
Figure 55. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update
Table 31. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h)
Bit
Field
Type
Reset
Description
7
PWR_DWN_STATUS
R
1’b0
Power Down Status Bit.
0 = Normal Operation (default)
1 = Device in Power Down Mode



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