PCF85263ATLSLASHA datasheet(27/102 Pages) NXP

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NXP Semiconductors

PCF85263A

Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus

The Watchdog counts down from a software-loaded 5-bit binary value, WDR[4:0], in register Watchdog. Loading

the counter with 0 stops the Watchdog. Loading the counter with a non-0 value starts the counter. Values from 1

to 31 are allowed.

aaa-009584

WDR counts

countdown value, WDR

Watchdog clock

counter

WDF

INTA or INTB

duration of first Watchdog period after start

may range from WDR to WDR -1 counts

In this example, it is assumed that the Watchdog flag (WDF) is cleared before the next Watchdog period expires and that

the interrupt output is set to pulsed mode.

Figure 15. Watchdog repeat mode

If a new value of WDR[4:0] is written before the end of the current Watchdog period, then this value takes

immediate effect.

When starting the timer for the first time or when reloading WDR[4:0] before the end of the current period, the

first period has an uncertainty of maximum one count. The uncertainty is a result of loading the WDR[4:0] from

the interface clock, which is asynchronous from the Watchdog source clock. Subsequent Watchdog periods do

not have such variation.

Reading the Watchdog register returns the current value of the Watchdog counter (for details, see Figure 15)

and

not the initial value WDR[4:0]. Since it is not possible to freeze the Watchdog counter during read back, it is

recommended to read the register twice and check for consistent results.

7.5.1.1 Watchdog repeat mode

In repeat mode, at the end of every Watchdog period, the Watchdog flag (bit WDF in the flags register,

Section 7.14) is set and the counter automatically reloads and starts the next Watchdog period. An example is

given in Figure 15. The asserted bit WDF can be used to generate an interrupt. Only a command can clear Bit

WDF.

7.5.1.2 Watchdog single shot mode

In single shot mode, at the end of the countdown period, the Watchdog flag (bit WDF in the flags register,

Section 7.14) is set and the counter stops with the value 0. The Watchdog register must be reloaded to start

another Watchdog period.

PCF85263A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.4 — 12 December 2025

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