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PCF85263ATL/A Datasheet(PDF) 98 Page - NXP Semiconductors

Part # PCF85263ATL/A
Description  Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus
PDF  102 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF85263ATL/A Datasheet(HTML) 98 Page - NXP Semiconductors

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NXP Semiconductors
PCF85263A
Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus
Tables
Tab. 1.
Ordering information ..........................................5
Tab. 2.
Ordering options ................................................5
Tab. 3.
Pin description ...................................................8
Tab. 4.
RTC mode time registers ................................ 11
Tab. 5.
Stop-watch mode time registers ......................12
Tab. 6.
Control and function registers overview .......... 13
Tab. 7.
Time and date registers in RTC mode
(RTCM = 0) .....................................................14
Tab. 8.
BCD coding .....................................................15
Tab. 9.
Weekday assignments .................................... 16
Tab. 10. Month assignments in BCD format ..................16
Tab. 11. Time registers in stop-watch mode (RTCM
= 1) ..................................................................18
Tab. 12. Alarm1 and alarm2 registers in RTC mode
coded in BCD (RTCM = 0) ..............................19
Tab. 13. Alarm_enables- alarm enable control
register (address 10h) bit description .............. 20
Tab. 14. Alarm1 and alarm2 registers in stop-watch
mode coded in BCD (RTCM = 1) ....................23
Tab. 15. Alarm_enables- alarm enable control
register (address 10h) bit description .............. 23
Tab. 16. Watchdog - Watchdog control and register
(address 2Dh) bit description .......................... 26
Tab. 17. Watchdog durations ........................................ 26
Tab. 18. RAM_byte - 8-bit RAM register (address
2Ch) bit description ......................................... 28
Tab. 19. TSR_mode - timestamp mode control
register (address 23h) bit description .............. 29
Tab. 20. Timestamp registers in RTC mode (RTCM
= 0) ..................................................................31
Tab. 21. Timestamp registers in stop-watch mode
(RTCM = 1) .....................................................32
Tab. 22. Offset - offset register (address 24h) bit
description ....................................................... 33
Tab. 23. OFFM bit - oscillator control register
(address 25h) .................................................. 33
Tab. 24. Offset values ................................................... 33
Tab. 25. Correction pulses for OFFM = 0 ......................34
Tab. 26. Correction pulses for OFFM = 1 ......................35
Tab. 27. INTA and INTB interrupt control bits ................37
Tab. 28. Definition of interrupt control bits .....................37
Tab. 29. Oscillator - oscillator control register
(address 25h) bit description ...........................41
Tab. 30. CLKIV bit - oscillator control register
(address 25h) .................................................. 41
Tab. 31. 12_24 bit - oscillator control register
(address 25h) .................................................. 41
Tab. 32. LOWJ bit - oscillator control register
(address 25h) .................................................. 41
Tab. 33. OSCD[1:0] bits - oscillator control register
(address 25h) .................................................. 42
Tab. 34. CL[1:0] bits - oscillator control register
(address 25h) .................................................. 42
Tab. 35. IO pin behavior in battery mode ......................43
Tab. 36. Battery_switch - battery switch control
(address 26h) bit description ...........................43
Tab. 37. BSOFF bit - battery switch control (address
26h) bit description ..........................................43
Tab. 38. BSRR bit - battery switch control (address
26h) bit description ..........................................43
Tab. 39. BSM[1:0] bits - battery switch control
(address 26h) bit description ...........................44
Tab. 40. Battery switch-over modes ..............................44
Tab. 41. BSTH - battery switch control (address
26h) bit description ..........................................48
Tab. 42. Pin_IO- pin input output control register
(address 27h) bit description ...........................48
Tab. 43. CLKPM bit - Pin_IO control register
(address 27h) .................................................. 48
Tab. 44. TSPULL bit - Pin_IO control register
(address 27h) .................................................. 49
Tab. 45. TSL bit - Pin_IO control register (address
27h) ................................................................. 49
Tab. 46. TSPM[1:0] bits - Pin_IO control register
(address 27h) .................................................. 49
Tab. 47. TSIM bit - Pin_IO control register (address
27h) ................................................................. 50
Tab. 48. INTAPM[1:0] bits - Pin_IO control register
(address 27h) .................................................. 51
Tab. 49. INTA battery mode .......................................... 52
Tab. 50. Function - chip function control register
(address 28h) bit description ...........................52
Tab. 51. 100TH bit - Function control register
(address 28h) .................................................. 52
Tab. 52. PI[1:0] bits - Function control register
(address 28h) .................................................. 52
Tab. 53. RTCM bit - Function control register
(address 28h) .................................................. 53
Tab. 54. RTC time counting modes ...............................53
Tab. 55. STOPM bit - Function control register
(address 28h) .................................................. 53
Tab. 56. Oscillator stop control when STOPM = 1 .........53
Tab. 57. COF[2:0] bits - Function control register
(address 28h) .................................................. 54
Tab. 58. Clock duty cycles ............................................ 54
Tab. 59. Flags - Flag status register (address 2Bh)
bit description .................................................. 55
Tab. 60. Reset - software reset control (address
2Fh) bit description ......................................... 56
Tab. 61. Registers reset values .....................................57
Tab. 62. Stop_enable - control of STOP bit (address
2Eh) .................................................................58
Tab. 63. Counter stop signal ......................................... 59
Tab. 64. I2C target address byte ...................................64
Tab. 65. Application configuration ................................. 65
Tab. 66. Limiting values ................................................ 69
Tab. 67. Characteristics .................................................70
Tab. 68. I2C-bus characteristics ....................................74
Tab. 69. SnPb eutectic process (from J-STD-020D) ..... 87
Tab. 70. Lead-free process (from J-STD-020D) ............87
Tab. 71. Acronyms .........................................................92
Tab. 72. Revision history ...............................................94
PCF85263A
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.4 — 12 December 2025
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