PCF85263ATLSLASHA datasheet(41/102 Pages) NXP

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NXP Semiconductors

PCF85263A

Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus

7.10 Oscillator register

Bit

Symbol

CLKIV

OFFM

12_24

LOWJ

OSCD[1:0]

CL[1:0]

Section

Section 7.16

Section 7.8

Section 7.10.3

Section 7.10.4

Section 7.10.5

Section 7.10.6

Table 29. Oscillator - oscillator control register (address 25h) bit description

7.10.1 CLKIV: Invert the clock output

Bit

Symbol

Value

Description

Output clock inversion

0 [1]

Non-inverting; LOWJ mode affects rising edge

CLKIV

Inverted; LOWJ mode affects falling edge

Table 30. CLKIV bit - oscillator control register (address 25h)

[1]

Default value.

The clock selected with the COF[2:0] bits (register Function, address 28h) can be inverted. This is intended for

use with the low jitter mode, LOWJ. The low jitter mode reduces the jitter for the rising edge of the output clock.

If the reduced jitter must be on the falling edge (like when using an open-drain clock output), the CLKIV bit can

be used to implement it.

7.10.2 OFFM: Offset calibration mode

See Section 7.8 for a full description of offset calibration.

7.10.3 12_24: 12 hour or 24 hour clock

Bit

Symbol

Value

Description

12 hour or 24 hour mode

0 [1]

24 hour mode is selected

12_24

12 hour mode is selected

Table 31. 12_24 bit - oscillator control register (address 25h)

[1]

Default value.

In RTC mode, time counting can be configured for a 24 hour clock or 12 hour clock with the AMPM flag.

This bit is ignored in stop-watch mode.

7.10.4 LOWJ: Low jitter mode

Bit

Symbol

Value

Description

Low jitter CLK output bit

0 [1]

Normal

LOWJ

Reduced CLK output jitter; increase IDD

Table 32. LOWJ bit - oscillator control register (address 25h)

PCF85263A

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Product data sheet

Rev. 5.4 — 12 December 2025

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