PCF85263ATLSLASHA datasheet(48/102 Pages) NXP

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NXP Semiconductors

PCF85263A

Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus

7.11.4 BSTH: Threshold voltage control

Bit

Symbol

Value

Description

Battery switch threshold voltage, Vth

0 [1]

Vth = 1.5 V

BSTH

Vth = 2.8 V

Table 41. BSTH - battery switch control (address 26h) bit description

[1]

Default value.

The threshold for battery switch-over is selectable between two voltages, 1.5 V and 2.8 V.

7.11.5 Battery switch interrupts

The generation of interrupts from the battery switch function is controlled via the battery switch interrupt enable

bits; BSIEA and BSIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address

2Ah).

The assertion of the flag BSF (register Flags, address 2Bh) can be used to generate an interrupt at pins INTA

and INTB. The interrupt can be generated as a pulsed signal or alternatively as a permanently active signal,

which follows the condition of bit BSF. BSF remains set until cleared by command.

When enabled, interrupts are triggered every time the battery switch circuit switches to either battery or to VDD

and even if the BSF is not cleared, an interrupt pulse can be generated.

In addition, the INTA pin can be configured as a battery mode indicator (INTAPM[1:0] = 00). See Section 7.12.6.

This mode differs from a general interrupt signal in that it is only controlled by the current battery switch status.

See Section 7.9 for interrupt control.

Remark: INTB pin is only active when the IC is operating from VDD.

7.12 Pin_IO register

Bit

Symbol

CLKPM

TSPULL

TSL

TSIM

TSPM[1:0]

INTAPM[1:0]

Section

Section 7.12.1

Section 7.12.2

Section 7.12.3

Section 7.12.5

Section 7.12.4

Section 7.12.6

Table 42. Pin_IO- pin input output control register (address 27h) bit description

This register is used to define the input and output modes of the IC.

7.12.1 CLKPM: CLK pin mode control

Bit

Symbol

Value

Description

CLK pin mode

0 [2]

Enable CLK pin

CLKPM [1]

Disable CLK pin

Table 43. CLKPM bit - Pin_IO control register (address 27h)

[1]

CLK pin is not available in all package types.

[2]

Default value.

PCF85263A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.4 — 12 December 2025

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PCF85263ATL/A Datasheet(PDF) 48 Page - NXP Semiconductors

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