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PCF85263ATL/A Datasheet(PDF) 37 Page - NXP Semiconductors |
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PCF85263ATL/A Datasheet(HTML) 37 Page - NXP Semiconductors |
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37 / 102 page  NXP Semiconductors PCF85263A Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus 7.8.4 Offset interrupts The generation of interrupts from the offset functions is controlled via the offset interrupt enable bits; OIEA and OIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). Every time a correction pulse is made, an interrupt pulse can be generated at pins INTA and INTB. As there is no offset calibration flag, it is only possible to generate pulse interrupts. See Section 7.9 for interrupt control. 7.9 Interrupts There are two interrupt output pins, INTA and INTB. Both pins have the same possible sources and a dedicated register to control what is output. The pins can be used independently from each other. INTA data is output on the INTA pin. INTA is an interrupt output pin with an open-drain drive. INTA pin mode is controlled by INTAPM[1:0] bits in the Pin_IO register (Section 7.12). INTB data is output on TS pin with push-pull drive. The TS pin must first be configured as INTB output by setting TSIO[1:0] bits in the Pin_IO register (Section 7.12). Interrupts will only be output when the pin mode is correctly defined. Interrupts are output from the IC as active LOW signals. The registers INTA_enable (address 29h) and INTB_enable (address 2Ah) are used to select which interrupts are output on which pin. Bit 7 6 5 4 3 2 1 0 INTA_enable - INTA pin enable control (address 29h) Symbol ILPA PIEA OIEA A1IEA A2IEA TSRIEA BSIEA WDIEA INTB_enable - INTB pin enable control (address 2Ah) Symbol ILPB PIEB OIEB A1IEB A2IEB TSRIEB BSIEB WDIEB Table 27. INTA and INTB interrupt control bits Symbol Bit INTA INTB Value Description Level or pulse mode 0 [1] Interrupt generates a pulse 7 ILPA ILPB 1 Interrupt follows flags (permanent signal) Periodic interrupt enable 0 [1] No periodic interrupt generated 6 PIEA PIEB 1 Periodic interrupt generated Offset correction interrupt enable 0 [1] No correction interrupt generated 5 OIEA OIEB 1 Interrupt generated from correction Alarm1 interrupt enable 4 A1IEA A1IEB 0 [1] No alarm interrupt generated Table 28. Definition of interrupt control bits PCF85263A All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 5.4 — 12 December 2025 Document feedback 37 / 102 |
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