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PCF85263ATL/A Datasheet(PDF) 43 Page - NXP Semiconductors |
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PCF85263ATL/A Datasheet(HTML) 43 Page - NXP Semiconductors |
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43 / 102 page  NXP Semiconductors PCF85263A Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus Associated with the battery switch-over is the battery switch flag (BSF) in the flags register (for details, see Section 7.14). Whenever the IC switches to battery operation, the flag is set. The flag can only be read when operating from VDD power. However, an interrupt pulse or static LOW signal can be generated whenever switching to a battery. An interrupt pulse can also be generated when switching back to VDD power. Examples are given in Figure 25 and Figure 26. When switched to battery, the VDD power domain is disabled. This condition means that I2C pins are ignored and CLK output is disabled. Also, Hi-Z, TS pin output mode is disabled and Hi-Z, TS digital input is ignored and may be left floating. TS pin mechanical switch detector is active. INTA output is still active for interrupt output and battery switch indication, but disabled for clock output. IO pin (mode) VDD operation VBAT operation SCL Active input Disabled; may be left floating SDA Active input/output Disabled; may be left floating CLK Active output Disabled; Hi-Z TS (output mode) Active output Disabled; Hi-Z TS (digital input) Active input Disabled; may be left floating TS (mechanical switch input) Active input Active input INTA Active output Active interrupt output Table 35. IO pin behavior in battery mode Bit 7 6 5 4 3 2 1 0 Symbol - - - BSOFF BSRR BSM[1:0] BSTH Section - - - Section 7.11.1 Section 7.11.2 Section 7.11.3 Section 7.11.4 Table 36. Battery_switch - battery switch control (address 26h) bit description 7.11.1 BSOFF: Battery switch on/off control Bit Symbol Value Description Battery switch on/off 0 [1] Enable battery switch feature 4 BSOFF 1 Disable battery switch feature Table 37. BSOFF bit - battery switch control (address 26h) bit description [1] Default value. The battery switch circuit can be disabled when not used. This operation disables the circuit and saves power consumption. When disabled, connect VBAT and VDD together. 7.11.2 BSRR: Battery switch internal refresh rate Bit Symbol Value Description Battery switch refresh rate 3 BSRR 0 [1] Low Table 38. BSRR bit - battery switch control (address 26h) bit description PCF85263A All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 5.4 — 12 December 2025 Document feedback 43 / 102 |
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