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PCF85263ATL/A Datasheet(PDF) 33 Page - NXP Semiconductors |
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PCF85263ATL/A Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 102 page ![]() NXP Semiconductors PCF85263A Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus 7.7.1 Timestamps interrupts The generation of interrupts from the timestamp functions is controlled via the timestamp interrupt enable bits; TSRIEA and TSRIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). The loading of new information into one of the timestamp registers can be used to generate an interrupt at pins INTA and INTB. The interrupt can be generated as a pulsed signal every time the timestamp register updates or as a permanently active signal that follows the condition of timestamp flags, TSR1F to TSR3F. The timestamp flags remain set until cleared by command. When enabled, interrupts are triggered every time the timestamp register updates and even if the associated flag is not cleared, an interrupt pulse can be generated. See Section 7.9 for interrupt control. 7.8 Offset register The PCF85263A incorporates an offset register (address 24h) which can be used to implement several functions, such as: • Accuracy tuning • Aging adjustment • Temperature compensation Bit Symbol Value Description 7 to 0 OFFSET[7:0] See Table 24 Offset value Table 22. Offset - offset register (address 24h) bit description There are two modes that define the correction period, normal mode and fast mode. The normal mode is suitable for offset trimming. The fast mode is suitable for dynamic offset correction, for example, implementing a temperature correction. The fast mode consumes more current. Offset mode is defined by bit OFFM in the oscillator register (Section 7.10). See Section 7.10 Bit Symbol Value Description Offset mode bit 0 [1] Normal mode: correction is made every 4 hours; 2.170 ppm/step 6 OFFM 1 Fast mode: correction is made once every 8 minutes; 2.0345 ppm/step Table 23. OFFM bit - oscillator control register (address 25h) [1] Default value. For OFFM = 0, each LSB introduces an offset of 2.170 ppm. For OFFM = 1, each LSB introduces an offset of 2.0345 ppm. The offset value is coded in two's complement giving a range of +127 LSB to -128 LSB, see Table 24. OFFSET[7:0] Offset value in ppm Offset value in decimal Normal mode OFFM = 0 Fast mode OFFM = 1 011 1 1111 +127 +275.590 +258.3815 Table 24. Offset values PCF85263A All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 5.4 — 12 December 2025 Document feedback 33 / 102 |
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