PCF85263ATLSLASHA datasheet(62/102 Pages) NXP

62 / 102 page

NXP Semiconductors

PCF85263A

Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus

8.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH, is defined as the START condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP condition - P (for

details, see Figure 35).

8.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as logic 0. A not-

acknowledge is defined as logic 1.

When written to, the target will generate an acknowledge after the reception of each byte. After the

acknowledge, another byte can be transmitted. It is also possible to send a STOP or START condition.

When read from, the controller receiver must generate an acknowledge after the reception of each byte. When

the controller receiver no longer requires bytes to be the transmitter, it must generate a not-acknowledge. After

the not-acknowledge, either a STOP or START condition must be sent.

A detailed description of the I2C-bus specification is given in ref.[8].

PCF85263A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.4 — 12 December 2025

Document feedback

62 / 102

PCF85263ATL/A Datasheet(PDF) 62 Page - NXP Semiconductors