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PCF85263ATL/A Datasheet(PDF) 61 Page - NXP Semiconductors |
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PCF85263ATL/A Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 102 page  NXP Semiconductors PCF85263A Tiny RTC/Calendar with Alarm Function, Battery Switch-Over, Time Stamp Input, and I2C-bus 8 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pullup resistor. Data transfer can be initiated only when the bus is not busy. Both data and clock lines remain HIGH when the bus is not busy. The PCF85263A acts as a target receiver when being written to and as a target transmitter when being read from. Remark: When on VBAT power, the interface is not accessible. aaa-010487 Write ACK from target S A A A P target address + 0 write data write data write data A S A A A P read data read data read data A Read ACK from target ACK from target ACK from controller target address + 1 ACK from target ACK from target ACK from controller ACK from target Figure 34. I2C read and write protocol SCL SDA ACK ACK S P aaa-010489 SCL SDA bit7 bit0 ACK ACK S START condition STOP condition P ACK of 1st byte from target ACK of 2nd byte from target I2C read example I2C write example bit7 bit0 1st byte, target address with R/W = 0 write 2nd byte START condition STOP condition 1st byte, target address with R/W = 1 ACK of 1st byte from target ACK of 2nd byte from target bit7 bit0 bit7 bit0 read 2nd byte Figure 35. I2C read and write signaling 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line during this time are interpreted as STOP or START conditions. PCF85263A All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product data sheet Rev. 5.4 — 12 December 2025 Document feedback 61 / 102 |
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