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ADS5560 Datasheet(PDF) 6 Page - Texas Instruments

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Part # ADS5560
Description  16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
PDF  53 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5560 Datasheet(HTML) 6 Page - Texas Instruments

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ELECTRICAL CHARACTERISTICS (Continued)
ADS5560
ADS5562
SLWS207 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
Typical values are at 25
°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 V
PP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, default fine gain (1dB),internal reference mode, DDR
LVDS interface 0 dB fine gain
(1).
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling
rate = Max Rated, default fine gain (1dB), unless otherwise noted.
ADS5562
ADS5560
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
FIN = 3 MHz
85
90
FIN = 10 MHz
77
85
78
88
HD3
dBc
Third harmonic
FIN = 25 MHz
83
83
FIN = 30 MHz
80
79
FIN = 3 MHz
104
104
Worst harmonic
FIN = 10 MHz
102
102
other than HD2,
dBc
FIN = 25 MHz
100
101
HD3
FIN = 30 MHz
100
101
FIN = 3 MHz
84
88
THD
FIN = 10 MHz
75.5
83
76.5
86
Total harmonic
dBc
FIN = 25 MHz
82
81
distortion
FIN = 30 MHz
80
78
IMD
Two-tone
FIN1 = 5 MHz, FIN2 = 10 MHz
92
98
dBFS
intermodulation
each tone -7 dBFS
distortion
Voltage overload
Recovery to 1% for 6-dB
1
1
clock
recovery time
overload
cycles
(1)
Note that after reset, the device is initialized to 1 dB fine gain setting. For SFDR and SNR performance across fine gains, see Typical
Characteristics section.
6
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5560 ADS5562



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