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ADS5560 Datasheet(PDF) 25 Page - Texas Instruments |
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ADS5560 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 53 page ![]() ADS5560 ADS5562 www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008 Table 22. PIN ASSIGNMENTS – CMOS Mode (continued) PIN PIN NUMBER PIN NAME DESCRIPTION TYPE NUMBER OF PINS SDATA This pin functions as serial interface data input when RESET is low. I 28 1 It functions as STANDBY control pin when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100-k Ω pull-down resistor to DRGND. SEN This pin functions as serial interface enable input when RESET is low. I 27 1 It functions as CLKOUT edge programmability when RESET is tied high. See Table 6 for detailed information. The pin has an internal 100-k Ω pull-up resistor to DRVDD. OE Output buffer enable input, active high. I 7 1 The pin has an internal 100-k Ω pull-up resistor to DRVDD. DFS Data Format Select input. I 6 1 This pin sets the DATA FORMAT (Twos complement or Offset binary) and the LVDS/CMOS output mode type. See Table 7 for detailed information. The pin has an internal 100-k Ω pull-down resistor to DRGND. MODE Mode select input. I 23 1 This pin selects the Internal or External reference mode. See Table 8 for detailed information. The pin has an internal 100-k Ω pull-down resistor to AGND. CLKOUT CMOS output clock O 5 1 D0 CMOS output data D0 O 31 1 D1 CMOS output data D1 O 32 1 D2 CMOS output data D2 O 33 1 D3 CMOS output data D3 O 34 1 D4 CMOS output data D4 O 37 1 D5 CMOS output data D5 O 38 1 D6 CMOS output data D6 O 39 1 D7 CMOS output data D7 O 40 1 D8 CMOS output data D8 O 41 1 D9 CMOS output data D9 O 42 1 D10 CMOS output data D10 O 43 1 D11 CMOS output data D11 O 44 1 D12 CMOS output data D12 O 45 1 D13 CMOS output data D13 O 46 1 D14 CMOS output data D14 O 47 1 D15 CMOS output data D15 O 48 1 OVR Out-of-range indicator, CMOS level signal O 3 1 DRVDD Digital and output buffer supply I 2, 35 2 DRGND Digital and output buffer ground I 1, 36 2 UNUSED Unused pin in CMOS mode - 4 1 PAD Connect the PAD to the ground plane. See in application section. 1 NC Do not connect - 21 1 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link(s): ADS5560 ADS5562 |
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