ADS5560 datasheet(32/53 Pages) TI

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Valid Up to Max Clock Rate (ADS5562 or ADS5560)

fIN − Input Frequency − MHz

100

G043

fS − Sampling Frequency − MSPS

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

CMOS, No-Load Capacitance

CMOS, 5-pF Load Capacitance

CMOS, 10-pF Load Capacitance

LVDS

G044

ADS5560

ADS5562

SLWS207 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS (continued)

Typical values are at 25

°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 V

PP clock

amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine

gain (1dB), (unless otherwise noted)

CMRR vs Common-Mode Frequency

Figure 42.

Power Dissipation vs Sampling Frequency

Figure 43.

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ADS5560 Datasheet(PDF) 32 Page - Texas Instruments

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