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ADS5560 Datasheet(PDF) 23 Page - Texas Instruments

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Part # ADS5560
Description  16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
PDF  53 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5560 Datasheet(HTML) 23 Page - Texas Instruments

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ADS5560
ADS5562
www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008
Table 21. PIN ASSIGNMENTS – LVDS Mode (continued)
PIN
PIN
NUMBER
PIN NAME
DESCRIPTION
TYPE
NUMBER
OF PINS
SCLK
This pin functions as serial interface clock input when RESET is low.
I
29
1
It functions as LOW SPEED MODE control when RESET is tied high.
See Table 4 for detailed information.
The pin has an internal 100-k
Ω pull-down resistor to DRGND.
SDATA
This pin functions as serial interface data input when RESET is low.
I
28
1
It functions as STANDBY control pin when RESET is tied high.
See Table 5 for detailed information.
The pin has an internal 100-k
Ω pull-down resistor to DRGND.
SEN
This pin functions as serial interface enable input when RESET is low.
I
27
1
It functions as CLKOUT edge programmability when RESET is tied
high. See Table 6 for detailed information.
The pin has an internal 100-k
Ω pull-up resistor to DRVDD.
OE
Output buffer enable input, active high.
I
7
1
The pin has an internal 100-k
Ω pull-up resistor to DRVDD.
DFS
Data Format Select input.
I
6
1
This pin sets the DATA FORMAT (Twos complement or Offset binary)
and the LVDS/CMOS output mode type. See Table 7 for detailed
information.
The pin has an internal 100-k
Ω pull-down resistor to DRGND.
MODE
Mode select input.
I
23
1
This pin selects the Internal or External reference mode. See Table 8
for detailed information.
The pin has an internal 100-k
Ω pull-down resistor to AGND.
CLKOUTP
Differential output clock, true
O
5
1
CLKOUTM
Differential output clock, complement
O
4
1
D0_D1_P
Differential output data D0 and D1 multiplexed, true
O
32
1
D0_D1_M
Differential output data D0 and D1 multiplexed, complement.
O
31
1
D2_D3_P
Differential output data D2 and D3 multiplexed, true
O
34
1
D2_D3_M
Differential output data D2 and D3 multiplexed, complement
O
33
1
D4_D5_P
Differential output data D4 and D5 multiplexed, true
O
38
1
D4_D5_M
Differential output data D4 and D5 multiplexed, complement
O
37
1
D6_D7_P
Differential output data D6 and D7 multiplexed, true
O
40
1
D6_D7_M
Differential output data D6 and D7 multiplexed, complement
O
39
1
D8_D9_P
Differential output data D8 and D9 multiplexed, true
O
42
1
D8_D9_M
Differential output data D8 and D9 multiplexed, complement
O
41
1
D10_D11_P
Differential output data D10 and D11 multiplexed, true
O
44
1
D10_D11_M
Differential output data D10 and D11 multiplexed, complement
O
43
1
D12_D13_P
Differential output data D12 and D13 multiplexed, true
O
46
1
D12_D13_M
Differential output data D12 and D13 multiplexed, complement
O
45
1
D14_D15_P
Differential output data D14 and D15 multiplexed, true
O
48
1
D14_D15_M
Differential output data D14 and D15 multiplexed, complement
O
47
1
OVR
Out-of-range indicator, CMOS level signal
O
3
1
DRVDD
Digital and output buffer supply
I
2, 35
2
DRGND
Digital and output buffer ground
I
1, 36
2
PAD
Connect the PAD to the ground plane. See in application section.
1
NC
Do not connect
-
21
1
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS5560 ADS5562



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