ADS5560 datasheet(19/53 Pages) TI

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ADS5560

ADS5562

www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008

Table 14.

A7 - A0 (hex)

<GAIN> FINE GAIN 0 dB to 6 dB, in 1 dB steps

D3 - D0

<GAIN> Programmable Fine Gain

0XXX

1 dB

1000

0 dB

1001

1 dB, default register value after reset

1010

2 dB

1011

3 dB

1100

4 dB

1101

5 dB

1110

6 dB

Table 15.

A7 - A0 (hex)

<CUSTOM A> CUSTOM PATTERN (D7 TO D0)

<CUSTOM B> CUSTOM PATTERN (D15 TO D8)

Reg 69

D7 - D0

Program bits D7 to D0 of custom pattern

Reg 6A

D15 - D8

Program bits D15 to D8 of custom pattern

Table 16.

A7 - A0 (hex)

<ODI> OUTPUT DATA

INTERFACE - DDR LVDS OR

PARALLEL CMOS

D4 - D3

<ODI> Output Interface

default after reset, state of DFS pin determines

interface type. See Table 7.

DDR LVDS outputs, independent of state of DFS

pin.

Parallel CMOS outputs, independent of state of

DFS pin.

Table 17.

A7 - A0

<REF>

INTERNAL or EXTERNAL

REFERENCE

<REF> Reference

Internal reference

External reference mode, force voltage on VCM to set reference.

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