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ES9039Q2M Datasheet(PDF) 53 Page - ESS Technology,Inc

Part # ES9039Q2M
Description  32-bit High Performance 2 Channel DAC
PDF  107 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9039Q2M Datasheet(HTML) 53 Page - ESS Technology,Inc

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VERSION 0.2.2
53
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
ES9039Q2M Product Datasheet
Timing Requirements
I²C Slave Interface Timing
Figure 20 - I²C Slave Control Interface Timing
Parameter
Symbol
CLK
Constraint
Standard-Mode
Fast-Mode
Unit
MIN
MAX
MIN
MAX
SCL Clock Frequency
fSCL
< CLK/20
0
100
0
400
kHz
START condition hold time
tHD;STA
4.0
-
0.6
-
s
LOW period of SCL
tLOW
>10/CLK
4.7
-
1.3
-
s
HIGH period of SCL (>10/CLK)
tHIGH
>10/CLK
4.0
-
0.6
-
s
START condition setup time (repeat)
tSU;STA
4.7
-
0.6
-
s
SDA hold time from SCL falling
-
All except NACK read
-
NACK read only
tHD;DAT
0
2/CLK
-
0
2/CLK
-
s
s
SDA setup time from SCL rising
tSU;DAT
250
-
100
-
ns
Rise time of SDA and SCL
tr
-
1000
300
ns
Fall time of SDA and SCL
tf
-
300
300
ns
STOP condition setup time
tSU;STO
4
-
0.6
-
s
Bus free time between transmissions
tBUF
4.7
-
1.3
-
s
Capacitive load for each bus line
Cb
-
400
-
400
pF
Table 30 - I²C Slave Interface Timing Definitions
Figure 21 - I²C Single Byte Examples of Read and Write Instructions
Start
Start
Start
Stop



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