ES9039Q2M datasheet(60/107 Pages) ESS

60 / 107 page

VERSION 0.2.2

ES9039Q2M Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

Bits

[7]

[6]

[5:0]

Default

1'b1

1'b0

6'd0

Bits

Mnemonic

Description

[7]

AUTO_FS_DETECT

Automatically determine optimal (SYS_CLK/CLK_IDAC ratio)

according to detected FS.

• 1'b0: Disabled, use reg 3[5:0] SELECT_IDAC_NUM to set

ratio.

• 1'b1: Enabled, overrides reg 3[5:0] SELECT_IDAC_NUM

(default)

Note: Cannot be used in ASYNC mode.

[6]

SELECT_IDAC_HALF

• 1'b0: Divide by SELECT_IDAC_NUM + 1 (default)

• 1'b1: Divide by half of SELECT_IDAC_NUM + 1

Note: Can only produce half of an odd number divide

[5:0]

SELECT_IDAC_NUM

CLK_IDAC divider. Whole number divide value + 1 for

CLK_IDAC (SYS_CLK/divide_value).

• 6'd0: Whole number divide value + 1 = 1

• 6'd1: Whole number divide value + 1 = 2

• 6'd63: Whole number divide value + 1 = 64

Bits

[7:0]

Default

8'd7

Bits

Mnemonic

Description

[7:0]

MASTER_BCK_DIV

Master mode clock divider. Whole number divide value + 1 for

CLK_Master (SYS_CLK/divide_value).

ES9039Q2M Datasheet(PDF) 60 Page - ESS Technology,Inc

ES9039Q2M Datasheet(HTML) 60 Page - ESS Technology,Inc

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