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CMV300 Datasheet(PDF) 23 Page - ams-OSRAM AG

Part # CMV300
Description  VGA resolution CMOS image sensor
PDF  56 Pages
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Manufacturer  AMSOSRAM [ams-OSRAM AG]
Direct Link  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

CMV300 Datasheet(HTML) 23 Page - ams-OSRAM AG

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Reference:CMV300-datasheet-v2.11
CMV300 Datasheet
Page 21 of 54
© 2016 CMOSIS bvba
4.1.2 LVDS READOUT TIMING
The readout of image data is grouped in bursts of 324 pixels per channel (2 rows at the same time). Each pixel is 12 bits
of data (see section 4.1.1). One complete pixel period equals one period of the master clock input. For details on pixel
remapping and pixel vs channel location please see section 4.1.3 of this document. An overhead time exists between
two bursts of 324 pixels. This overhead time has the length of one pixel read-out (i.e. the length of 12 bits at the selected
data rate) or one master clock cycle.
4.1.2.1 4 OUTPUT CHANNELS
By default, all 4 data output channels are used to transmit the image data. This means that two entire rows of image
data are transferred in one slot of 324 pixel periods (4 x 324 = 1296). Next figure shows the timing for the top and
bottom LVDS channels.
IDLE
OH
324
OH
DATA_OUT_TOP
324
OH
324
Row 1
Row 3
Row 5
IDLE
OH
324
OH
DATA_OUT_BOTTOM
324
OH
324
Row 2
Row 4
Row 6
FIGURE 17: OUTPUT TIMING IN DEFAULT 4 CHANNEL MODE
Only when 4 data outputs, running at 300Mbps, are used, the frame rate of 300fps can be achieved (default).
4.1.2.2 2 OUTPUT CHANNELS
The CMV300 has the possibility to use only 2 LVDS output channels. This setting can be programmed in the register with
address 57 (see section 5.7). In such multiplexed output mode, only the 2 bottom LVDS channels are used (channel 1
and channel 2). The readout of one row takes 1*324 periods. Next figure shows the timing for the bottom LVDS channels.
IDLE
OH
324
OH
324
OH
324
Row 1
Row 2
Row 3
DATA_OUT_BOTTOM
FIGURE 18: OUTPUT TIMING IN 2 CHANNEL MODE
In this 2 channel mode, the frame rate is reduced with a factor of 2 compared to 4 channel mode.
4.1.2.3 1 OUTPUT CHANNEL
The CMV300 has also the possibility to use only 1 LVDS output channel. This setting can be programmed in the register
with address 57 (see section 5.7). In such multiplexed output mode, only 1 of the bottom 2 LVDS channels is used
(channel 1) and the readout of one row takes 2*324 periods.
IDLE
OH
324
OH
324
OH
324
Row 1
Row 2
DATA_OUT_BOTTOM
OH
324
FIGURE 19: OUTPUT TIMING IN OF 1 CHANNEL MODE
In this 1 channel mode, the frame rate is reduced with a factor of 4 compared to 4 channel mode.
4.1.3 PIXEL REMAPPING
Depending on the number of output channels, the pixels are read out by different channels and come out at a different
moment in time. With the details from the next sections, the end user is able to remap the pixel values at the output to
their correct image array location.



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