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CMV300 Datasheet(PDF) 18 Page - ams-OSRAM AG

Part # CMV300
Description  VGA resolution CMOS image sensor
PDF  56 Pages
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Manufacturer  AMSOSRAM [ams-OSRAM AG]
Direct Link  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

CMV300 Datasheet(HTML) 18 Page - ams-OSRAM AG

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Reference:CMV300-datasheet-v2.11
CMV300 Datasheet
Page 16 of 54
© 2016 CMOSIS bvba
sensor is idle before read out starts.
When running the CMV300 sensor at 40MHz with 4 outputs and recommended FOT settings this results in: 105.625us.
������������������������������������������ ������������������������ = ������������������������ ������������������������ ∗
# ������������������������������
# ������������������������������ ������������������������
������������������������ ������������������������ =
2 ∗ 325 ∗ ������������������_������������������
# ������������������������������������ ������������������������������������������ ������������������������
When running the CMV300 sensor at 40MHz with 4 outputs and reading 480 lines this results in: 1950µs
This results in a total read-out time of 105.625us + 1950µs = 2.055625ms  486fps for 640 * 480 resolution.
3.7 START-UP SEQUENCE
The following sequence should be followed when the CMV300 is started up in default output mode (300Mbps, 12bit
resolution).
1μs
Stabelization time
Supply
CLK_IN
SYS_RES
Frame_REQ
1μs
FIGURE 4: START-UP SEQUENCE FOR 300MBPS @ 12-BIT
The master clock (25MHz for 300Mbps in 12-bit mode) should only start after the supplies are stable. The external reset
pin should be released at least 1μs after the supplies have become stable. The first frame can be requested 1μs after
the reset pin has been released. An optional SPI upload (to program the sequencer) is possible 1μs after the reset pin
has been released. In this case the FRAME_REQ pulse must be postponed until after the SPI upload has been completed.
When the CMV300 will be used in 8 or 10-bit mode or at another speed than 300mbps, an SPI upload is necessary to
program the sensor. In this case the start-up sequence looks like the diagram below. A PLL lock-time of 1ms should be
considered after uploading the register settings and before sending the FRAME_REQ pulse.
1μs
Stable time
Supply
CLK_IN
SYS_RES_N
FRAME_REQ
SPI settings
SPI upload
1μs
1ms
FIGURE 5: START-UP SEQUENCE FOR 8 OR 10 BIT MODE OR ANOTHER SPEED
The following SPI registers should be uploaded in this mode:



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