| Electronic Components Datasheet Search |
|
CMV300 Datasheet(PDF) 25 Page - ams-OSRAM AG |
|
|
|||||||||||||||||||||||||||||
CMV300 Datasheet(HTML) 25 Page - ams-OSRAM AG |
|
25 / 56 page ![]() Reference:CMV300-datasheet-v2.11 CMV300 Datasheet Page 23 of 54 © 2016 CMOSIS bvba Bit Function Description [0] DVAL Indicates valid pixel data on the outputs [1] LVAL Indicates validity of the readout of a row [2] FVAL Indicates the validity of the readout of a frame [3] FOT Indicates when the sensor is in FOT (sampling of image data in pixels) (*) [4] INTE1 Indicates when pixels of integration block 1 are integrating (*) [5] INTE2 Indicates when pixels of integration block 2 are integrating (*) [6] ‘0’ Constant zero [7] ‘1’ Constant one [8] ‘0’ Constant zero [9] ‘0’ Constant zero [10] ‘0’ Constant zero [11] ‘0’ Constant zero (*)Note: The status bits are purely informational. These bits are not required to know when the data is valid. The DVAL, LVAL and FVAL signals are sufficient to know when to sample the image data. Pin C6 (Test3 / CLK_OUT) can be programmed to map some control bits for easy measurement. Register 69 is used for this programming: Register 69 Value T_dig1 0 DVAL 1 LVAL 2 FVAL 6 FOT 7 INTE1 8 INTE2 9 CLK_OUT 4.1.4.1 DVAL, LVAL, FVAL The first three bits of the control word must be used to identify valid data and the readout status. Next figure shows the timing of the DVAL, LVAL and FVAL bits of the control channel with an example of the readout of a frame of 3 rows (default is 488 rows). This example uses the default mode of 4 outputs (2 outputs on each side). IDLE OH 324 OH 324 OH 324 DATA_OUT DVAL LVAL FVAL FIGURE 23: DVAL, LVAL AND FVAL TIMING IN 4 OUTPUT MODE When only 1 output (on one side) is used, the line read-out time is 2x longer. The control channel takes this into account and the timing in this mode looks like the diagram below. IDLE OH 324 OH 324 OH 324 DATA_OUT DVAL LVAL FVAL OH 324 OH 324 OH 324 FIGURE 24: DVAL, LVAL AND FVAL TIMING IN 1 OUTPUT MODE 4.1.5 TRAINING DATA The LVDS outputs are not perfectly edge aligned. This alignment has to be done in the receiving system. You can see the typical output skew in Figure 25. This skew is independent of the clock speed used. To synchronize the receiving side with the LVDS outputs of the CMV300, a known data pattern can be put on the output channels. This pattern can be |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |