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CMV300 Datasheet

Page 35 of 54

5.9 8-BIT, 10-BIT OR 12-BIT MODE

The CMV300 has the possibility to send 8 bits, 10 bits or 12 bits per pixel. The end user can select the desired resolution

by programming the corresponding sequencer register.

8-bit, 10-bit or 12-bit mode

Default value

Description of the value

Bit_mode

68[1:0]

0: 12 bits per pixel

1: 10 bits per pixel

2: 8 bits per pixel

The sensor will always output words of 12 bit length. So when changing to 10 or 8 bit, the LSB’s will be filled with 0’s.

This means that changing bit mode doesn’t affect the frame rate.

Bit mode

Decimal value

Output word

170

1010 1010 0000

10b

682

1010 1010 1000

12b

2730

1010 1010 1010

5.10 DATA RATE

During start-up or after a sequencer reset, the data rate can be changed if a lower speed than 480Mbps is desired. This

can be done by applying a lower master input clock (CLK_IN) to the sensor and uploading a new value in the PLL_range

data rate can be changed.

PLL range

Default value

Description of the value

PLL_range

155

155: CLK_IN is between 32MHz and 50MHz

187: CLK_IN is between 20MHz and 50MHz

251: CLK_IN is between 10 and 32MHz

The internal PLL has some temperature instabilities (full details are in errata sheet CMV300-ES2). The PLL cannot lock

after startup or reset at higher temperatures (resulting in an unstable output clock)(= instability 1) and the PLL can get

out of lock for a brief moment (~40µs) when the temperature increases/decreases during operation (=instability 2).

If you want to use the internal PLL without this issues occurring, you will be confined to some settings:

Keep the sensor temperature lower than 55°C (instability 1 will not occur)

Keep the temperature stable during operation (instability 2 will not occur)

You can set the input clock frequency above 32MHz (PLL range 187 or 155 see below) or 24MHz (PLL range

251) for instability 1 not to occur.

Only use PLL range of 155. Both instabilities should not occur with this setting. This will increase the minimum

frequency that can be used to 32MHz.

To decrease the output frame rate (caused by increasing the clock), you can increase the number of lines being read out

(reg1-2). This will increase the number of DVAL/LVAL blocks. The data of these rows outside the sensor pixel array will

not contain useable data. In the system these extra rows can just be discarded.

Also the PLL generates a higher jitter on the outputs (5-10%) then when using the LVDS input clock.

5.11 DISABLING THE INTERNAL PLL

When you do not want to use the internal PLL of the sensor, you can disable it and input an LVDS clock yourself. The

output data speed will then be equal to this clock speed, while the output LVDS clock will be half of the LVDS input clock

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