CMV300 datasheet(38/56 Pages) AMSOSRAM

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Reference:CMV300-datasheet-v2.11

CMV300 Datasheet

Page 36 of 54

(DDR). The LVDS_CLK_IN should be connected to pins D7 (LVDS_CLK_N) and D8 (LVDS_CLK_P) with a 100Ω parallel

termination resistor between the two pins. To disable the PLL set the following registers:

Set to value

Description of the value

PLL_ENABLE

83 [7]

0/1 = PLL disabled/enabled

I_LVDS_REC

82 [3:0]

LVDS Receiver strength

0 = off

LVDS_ENABLE

81 [6:0]

127

Enabled LVDS outputs:

Bit 0 = LVDS Input

Bit 1-4 = CH1-4 output

Bit 5 = LVDS CLK output

Bit 6 = CTR CH output

0/1 = Disabled/Enabled

CLK_LVDS_EXT

84 [0]

Selects the CLK_IN or LVDS_CLK as input clock

0 = CLK_IN

1 = LVDS_CLK_N/P

REG_CLK_SEL

63 [7]

Selects the PLL clock or the input clock

0 = PLL clock

1 = input clock

I_LVDS_DRIV

82 [7:4]

Sets the LVDS driver strength

0 = Off

1 – 15 = LVDS driver current

When you put in a LVDS_CLK_N/P clock of 430MHz, the LVDS output data rate will be 430Mbps (1 x 430MHz) with an

LVDS output clock of 215MHz (0.5 x 430MHz).

When using this mode, the maximum clock speed and therefor frame rate is lower than when using the internal PLL.

When disabling the PLL, the maximum LVDS input clock speed will be 430MHz, resulting in a frame rate of 430fps. See

Errata Sheet 2 for more detail on this speed limit.

5.12 POWER CONTROL

The power consumption of the CMV300 can be regulated by disabling the LVDS data channels when they are not used

(in 2 or 1 channel mode).

Power control

Default value

Description of the value

Channel_en

81[6:0]

126

Bit 1-2 enable/disable the bottom data output channels

Bit 3-4 enable/disable the top data output channels

Bit 5 enables/disables the output clock channel

Bit 6 enables/disables the control channel

Bit 0 enables/disables the optional LVDS clock input

channel

0: disabled

1: enabled

5.13 OFFSET AND GAIN

5.13.1 OFFSET

A digital offset can be applied to the output signal. A separate offset can be given to the data coming from the top

outputs and the data coming from the the bottom outputs. The dark level offset can be programmed by setting the

desired value in the sequencer registers. Dark-level @ output = ADC_output + Offset

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