CMV300 datasheet(27/56 Pages) AMSOSRAM

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Reference:CMV300-datasheet-v2.11

CMV300 Datasheet

Page 25 of 54

4.2 PARALLEL CMOS OUTPUT

When pin B2 is connected to GND, the CMV300 also has one 10 bit digital parallel CMOS output. On this output the

pixels of the image array are presented with a frequency of maximum 40MHz resulting in a frame rate of 120 fps. Next

to the data channels 3 additional CMOS channels are available for control and synchronization of the image data.



10 Data channels (bit[0] to bit[9], VDD20 CMOS)



2 Control channels (DVAL and LVAL, VDD20 CMOS)



1 Clock channel (CLK_OUT, 3.3V CMOS)

This means that a total of 13 pins of the CMV300 are used for the parallel CMOS output (10 for data + 2 for control

channel + 1 for clock channel). See the pin list for the exact pin numbers of the parallel CMOS output. The 10 data

channels are used to transfer the 10-bit pixel data from the sensor to the receiver in the surrounding system. The output

clock channel transports a clock, synchronous to the data on the data channels. Register 69 has to be set to 9 to output

this clock. This clock can be used at the receiving end to sample the data. The data on the control channels contains

status information on the validity of the data on the data channels.

4.2.1 PARALLEL OUTPUT TIMING

In parallel output mode, the readout of one row takes 2*324 periods. In this mode, the frame rate is reduced with a

factor of 4 compared to 4 LVDS channel mode. The figure below shows the timing for read-out of one line

Pixel 0

Pixel 1

CLK_OUT

DATA_OUT

Pixel 2

Pixel 322

Pixel 323

DVAL

Pixel 324

Pixel 325

Pixel 326

Pixel 646

Pixel 647

INVALID

LVAL

FIGURE 28: PARALLEL OUTPUT TIMING OF ONE LINE

The time of ‘T1’ from the figure above and below has the same length as the period of the CLK_IN signal. As can be

seen in the figure above it is advised to sample the parallel output data on the falling edge of the CLK_OUT.

The figure below details the LVAL and DVAL timing for a frame read-out of tree lines.

LVAL

DVAL

Row 1

Row 2

Row 3

FIGURE 29: LVAL/DVAL TIMING FOR A FRAME OF 3 LINES USING THE PARALLEL OUTPUT

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