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WM8959 Datasheet(PDF) 38 Page - Wolfson Microelectronics plc |
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WM8959 Datasheet(HTML) 38 Page - Wolfson Microelectronics plc |
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38 / 155 page  WM8959 Pre-Production w PP, May 2008, Rev 3.1 38 INPUT PGA ENABLE The Input PGAs are enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA and RIN34_ENA as described in Table 2. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7 LIN34_ENA (rw) 0b LIN34 Input PGA Enable 0 = disabled 1 = enabled 6 LIN12_ENA (rw) 0b LIN12 Input PGA Enable 0 = disabled 1 = enabled 5 RIN34_ENA (rw) 0b RIN34 Input PGA Enable 0 = disabled 1 = enabled R2 (02h) 4 RIN12_ENA (rw) 0b RIN12 Input PGA Enable 0 = disabled 1 = enabled Table 2 Input PGA Enable To enable the input PGAs, the reference voltage VMID and the bias current must also be enabled. See “Power Management” for definitions of the associated controls VMID_MODE and VREF_ENA. |
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