WM8959 datasheet(93/155 Pages) WOLFSON

93 / 155 page

Pre-Production

WM8959

PP, May 2008, Rev 3.1

These registers are described in Table 50 below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIF_MSTR1

Audio Interface 1 Master Mode Select

0 = Slave mode

1 = Master mode

AIF_MSTR2

Audio Interface 2 Master Mode Select

0 = Slave mode

1 = Master mode

R8 (08h)

AIF_SEL

Audio Interface Select

0 = Audio interface 1

1 = Audio interface 2 (GPIO3/BCLK2,

GPIO4/DACLRC2, GPIO5/DACDAT2)

R9 (09h)

DACLRC_DIR

DACLRC Direction

(Forces DACLRC clock to be output in

slave mode)

0 = DACLRC normal operation

1 = DACLRC clock output enabled

Table 50 Audio Interface Output Function Control

OPERATION WITH TDM

Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same

bus. The WM8959 DACs support TDM in master and slave modes, on both interfaces, and for all

data formats and word lengths. TDM is enabled using register bit AIFDAC_TDM. The TDM data slot

is programmed using register bit AIFDAC_TDM_CHAN.

WM8959

Processor

WM8959 or

Similar

DAC

DACDAT

DACLRC

BCLK

DACDAT

DACLRC

BCLK

Figure 60 TDM with WM8959 as Master

Figure 61 TDM with Other DAC as Master

WM8959 Datasheet(PDF) 93 Page - Wolfson Microelectronics plc

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