Rev. 0

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Page 12 of 42

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July 2023

AD2437

Digital I/O

IIH

8

Input Leakage, High

VIOVDD = 3.63 V, VIN = 3.63 V

10.0

μA

IIL

8

Input Leakage, Low

VIOVDD = 3.63 V, VIN = 0 V

10.0

μA

VOH1.9

8

High Level Output Voltage

VIOVDD = 1.70 V, IOH = 1 mA

1.35

V

VOH3.3

8

High Level Output Voltage

VIOVDD = 3.00 V, IOH = 1 mA

2.40

V

VOL

8

Low Level Output Voltage

VIOVDD = 3.00 V, IOL = 1 mA

0.40

V

VOL

8

Low Level Output Voltage

VIOVDD = 1.70 V, IOL = 1 mA

0.40

V

VOL_I2C

9

I

2C Low Level Output Voltage

VIOVDD = 3.00 V, IOL = 3.0 mA

0.40

V

VOL_I2C

10

I

2C Low Level Output Voltage

VIOVDD = 1.70 V, IOL = 1.0 mA

0.40

V

CPD

Pin Capacitance

5pF

Line Power Switch

Internal VSENSEP Currents

IVSENSEP

VVSENSEP

VVSENSEP = VVBUS = 24 V

400

μA

Internal ISENSEP Current

IISENSEP

VISENSEP

VVBUS – VISENSEP = 100 mV

13.0

18.0

22.5

μA

SWN Leakage Current

ISWN_LKG

VSWN_LGKG

VSWN = 3.3 V

3.2

mA

Current Thresholds

V

HSNS_LM = VVBUS – VISENSEP

High Side Current Limit Threshold

ON State

100

150

182

mV

V

LSNS_CF = VISENSEN – VVSENSEN Low Side Current Fault Threshold

ON State, VVSENSEN = 0.1 V

115

150

160

mV

External High Side NFET Gate Drive

VSWP – VVSENSEP

ON State, VVSENSEP = VVBUS

4.5

4.7

5.1

V

SWP Slew Rate With Soft Start Enabled11

V

SWP/dt

CAP_DLY = 0, VVBUS = 7 V

1.9

2.2

2.5

V/ms

CAP_DLY = 1, VVBUS = 7 V

9.5

11.6

12.8

V/ms

External Low Side NFET Gate Drive

VSWN

ON State, 220k pull-down to GND on SWN

4.1

V

1 Main node and last subordinate node only consume half the transceiver current because only one of the two transceivers is used.

2 I

IOVDD operational current depends on switching currents on digital I/O pins such as BCLK, SYNC, ADR1, ADR2, SCK, MISO, MOSI, SIOn, and GPIO7. Customers can

calculate the dynamic current using the formula: Output Dynamic Current = (CPD + CL) × VIOVDD × Switching Frequency.

3 I

VOUT1 = Max IDVDD + Max IPLLVDD and IVOUT2 = Max ITRXVDD + Typ IIOVDD. The typical IOVDD current for I

2S at 25 MHz is 15 mA, with a standard capacitive load of 6 pF

(average) on all pins.

4 The chip reset signal is asserted when any supply voltage drops below the reset assertion threshold.

5 The transceiver comes out of reset when all the power supply and the reset pin voltages are above the reset deassertion threshold.

6 IVOUT1 + IVOUT2 < 30 mA when VIN is bus powered by a current limiting device like the ADP2360 from the upstream node.

7 Refer to the VREG Safe Operating Area section.

8 Applies to ADR1, ADR2, SCK, MISO, MOSI, SIOn, BCLK, SYNC, IRQ, and GPIO7 pins.

9 Applies to SDA and SCL pins in standard mode, fast mode, and fast mode plus.

10Applies to SDA and SCL pins in fast mode and fast mode plus.

11Applies when not in current limit with large capacitor bus loading.

Parameter

Conditions

Min

Typ

Max

Unit