AD2437 datasheet(24/42 Pages) AD

24 / 42 page

Rev. 0

Page 24 of 42

July 2023

AD2437

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 11 and Figure 21 describe serial peripheral interface (SPI) port slave operations.

Table 11. Serial Peripheral Interface (SPI) Port—Slave Timing

IOVDD = 1.8 V

IOVDD = 3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tSCKS

SCK Period

66.67

tSCKHS

SCK High Period

tSCKLS

SCK Low Period

tSMOSI

Data Input Valid to SCK Sample Edge (Data Input Setup)

2.0

1.0

tHMOSI

SCK Sample Edge to Data Input Invalid (Data Input Hold)

1.8

0.5

tSSS

SPISS Assertion to First SCK Edge

7.0

8.0

tHSS

Last SCK Edge to SPISS Deassertion

10.75

9.75

tSSPWS

SPISS Pulse Width High (Inactive State Between Transfers)

Switching Characteristics

tDSSOE

SPISS Assertion to Data Out Active

4.50

28.50

2.50

17.50

tDSSHI

SPISS Deassertion to Data Out High Impedance

1.25

22.00

1.25

12.75

tDMISO

SCK Drive Edge to Data Out Valid (Data Out Delay)

19.50

10.75

tHDMISO

SCK Drive Edge to Data Out Invalid (Data Out Hold)

2.50

3.50

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