455A datasheet(34/148 Pages) RENESAS

34 / 148 page

Rev.1.01

Feb 15, 2008

Page 34 of 146

REJ03B0224-0101

455A Group

Note 1. “R” represents read enabled, and “W” represents write enabled.

Note 2. This function is valid only when the timer 1 control start synchronous circuit is selected (I10 =“1”).

Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.

Table 17 Timer control registers

Timer control register PA

at reset : 02

at power down : 02

TPAA

PA0

Prescaler control bit

Stop (state retained)

1Operating

Timer control register W1

at reset : 00002

at power down : state retained

R/W

TAW1/TW1A

W13

Timer 1 count auto-stop circuit selection bit

(Note 2)

Timer 1 count auto-stop circuit not selected

Timer 1 count auto-stop circuit selected

W12 Timer 1 control bit

Stop (state retained)

1Operating

Timer 1 count source selection bits (Note 3)

W11 W10

Count source

W11

PWM signal (PWMOUT)

Prescaler output (ORCLK)

Timer 3 underflow signal (T3UDF)

W10

CNTR input

Timer control register W2

at reset : 00002

at power down : 00002

R/W

TAW2/TW2A

W23 CNTR pin function control bit

CNTR pin output invalid

CNTR pin output valid

W22

PWM signal

“H” interval expansion function control bit

PWM signal “H” interval expansion function invalid

PWM signal “H” interval expansion function valid

W21 Timer 2 control bit

Stop (state retained)

1Operating

W20 Timer 2 count source selection bit

0XIN input

Prescaler output (ORCLK)/2

Timer control register W3

at reset : 00002

at power down : state retained

R/W

TAW3/TW3A

W33 Timer 3 control bit

Stop (initial state)

Operating

W32

Timer 3 count value selection bits

W32 W31 W30

Count value

000

Underflow every 512 count

001

Underflow every 1024 count

W31

010

Underflow every 2048 count

011

Underflow every 4096 count

100

Underflow every 8192 count

W30

101

Underflow every 16384 count

110

Underflow every 32768 count

111

Underflow every 65536 count

Timer control register W4

at reset : 00002

at power down : state retained

R/W

TAW4/TW4A

W43 Timer LC control bit

Stop (state retained)

1Operating

W42 Timer LC count source selection bit

0Bit 4 (T34) of timer 3

System clock (STCK)

W41

CNTR pin output auto-control circuit

selection bit

CNTR output auto-control circuit not selected

CNTR output auto-control circuit selected

W40 CNTR pin input count edge selection bit

Falling edge

Rising edge

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