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455A Datasheet(PDF) 10 Page - Renesas Technology Corp |
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455A Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 148 page  Rev.1.01 Feb 15, 2008 Page 10 of 146 REJ03B0224-0101 455A Group Fig 4. Port block diagram (2) Register Y Decoder SD instruction RD instruction CLD instruction (Note 1) (Note 1) XCIN/D6 (Note 2) S R Q RG2 1 0 Register Y Decoder SD instruction RD instruction CLD instruction (Note 1) (Note 1) XCOUT/D7 (Note 2) S R Q RG2 1 0 Quartz-crystal oscillation circuit Sub-clock input RG2 (Note 1) (Note 1) C/CNTR (Note 2) SCP instruction RCP instruction S R Q PWMOD D T Q R Timer 1 underflow signal W41 W12 W10 W11 Clock input for timer 1 event count Key-on wakeup input Pull-up transistor SZD instruction Skip decision Edge detection circuit PU33 K33 Pull-up transistor PU33 SZD instruction Skip decision Key-on wakeup input Edge detection circuit K33 Notes 1. This symbol represents a parasitic diode on the port. 2. Applied potential to these ports must be VDD or less. |
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