455A datasheet(27/148 Pages) RENESAS

27 / 148 page

Rev.1.01

Feb 15, 2008

Page 27 of 146

REJ03B0224-0101

455A Group

EXTERNAL INTERRUPTS

The 455A Group has the external 0 interrupt. An external

interrupt request occurs when a valid waveform is input to an

interrupt input pin (edge detection).

The external interrupt can be controlled with the interrupt control

Fig 28. External interrupt circuit structure

Table 14 External interrupt activated conditions

Name

Input pin

Activated condition

Valid waveform

selection bit

External 0 interrupt

D5/INT

When the next waveform is input to D5/INT pin

• Falling waveform (

“H” → “L”)

• Rising waveform (

“L” → “H”)

• Both rising and falling waveforms

I11

I12

Key-on wakeup input

SNZI0 instruction

(Note 1)

K21

Edge detection circuit

Level detection circuit

D5/INT

I13

I12

Falling

Rising

K20

I11

One-sided edge

detection circuit

Both edges

detection circuit

Skip

EXF0

External 0

interrupt

Timer 1 count start

synchronization

circuit input

(Note 2)

(Note 3)

Note 1:

This symbol represents a parasitic diode on the port.

2: When

I12= 0(X=0 or 1) is 0, “L” level is detected.

When I12 is 1, “H” level is detected.

3: When I12 is 0, falling edge is detected.

When I12 is 1, rising edge is detected.

(Note 1)

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