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4518 Datasheet(PDF) 147 Page - Renesas Technology Corp

Part # 4518
Description  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  160 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4518 Datasheet(HTML) 147 Page - Renesas Technology Corp

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Rev.3.01
2005.06.15
page 147 of 157
REJ03B0008-0301
4518 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
VDD
VDD
VDD
VRAM
VSS
VIH
VIH
VIH
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
IOL(avg)
IOL(avg)
ΣIOH(avg)
ΣIOL(avg)
Parameter
Supply voltage
(when ceramic resonator/
on-chip oscillator is used)
Supply voltage
(when RC oscillation is used)
Supply voltage
(when quartz-crystal oscillator is used)
RAM back-up voltage
Supply voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“H” level peak output current
“H” level average output current
(Note)
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level average output current
(Note)
“L” level average output current
(Note)
“L” level average output current
(Note)
“L” level average output current
(Note)
“H” level total average current
“L” level total average current
Note: The average output current is the average value during 100 ms.
Unit
Conditions
Mask ROM version
One Time PROM version
f(STCK)
≤ 4.4 MHz
Mask ROM version
One Time PROM version
Mask ROM version
One Time PROM version
P0, P1, P2, P3, P6, D0–D7, VDCE, XIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
P0, P1, P2, P3, P6, D0–D7, VDCE, XIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
P0, P1, D0–D7
CNTR0, CNTR1
P0, P1, D0–D7
CNTR0, CNTR1
P0, P1, P2, P6
SCK, SOUT
P3, RESET
D0–D5
D6, D7
CNTR0, CNTR1
P0, P1, P2, P6
SCK, SOUT
P3, RESET
D0–D5
D6, D7
CNTR0, CNTR1
D0–D7, CNTR0, CNTR1
P0, P1
P2, D0–D7, RESET, CNTR0, CNTR1
P0, P1, P3, P6
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VDD
VDD
VDD
0.2VDD
0.3VDD
0.15VDD
–20
–10
–10
–5
24
12
10
4
24
12
40
30
12
6
5
2
15
7
30
15
–60
–60
80
80
Limits
Min.
4.0
2.7
2.0
1.8
4.0
2.7
2.5
2.7
2.0
2.5
1.6
2.0
0.8VDD
0.85VDD
0.85VDD
0
0
0
Typ.
0
f(STCK)
≤ 6 MHz
f(STCK)
≤ 4.4 MHz
f(STCK)
≤ 2.2 MHz
f(STCK)
≤ 1.1 MHz
f(STCK)
≤ 6 MHz
f(STCK)
≤ 4.4 MHz
f(STCK)
≤ 2.2 MHz
f(XIN)
≤ 50 kHz
f(XIN)
≤ 50 kHz
at RAM back-up mode
at RAM back-up mode
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA



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