SH7136 datasheet(117/1160 Pages) RENESAS

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Section 5 Exception Handling

Rev. 2.00 Sep. 10, 2008 Page 91 of 1130

REJ09B0402-0200

5.8.4

Notes on Slot Illegal Instruction Exception Handling

Some specifications on slot illegal instruction exception handling in this LSI differ from those of

the conventional SH-2.

• Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot

illegal instructions.

• This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal

instructions.

The supporting status on our software products regarding this note is as follows:

Compiler

This instruction is not allocated in the delay slot in the compiler V.4 and its subsequent versions.

Real-time OS for

µITRON specifications

1. HI7000/4, HI-SH7

This instruction does not exist in the delay slot within the OS.

2. HI7000

This instruction is in part allocated to the delay slot within the OS, which may cause the slot

illegal instruction exception handling in this LSI.

3. Others

The slot illegal instruction exception handling may be generated in this LSI in a case where the

instruction is described in assembler or when the middleware of the object is introduced.

Note that a check-up program (checker) to pick up this instruction is available on our website.

Download and utilize this checker as needed.

SH7136 Datasheet(PDF) 117 Page - Renesas Technology Corp