SH7136 datasheet(129/1160 Pages) RENESAS

129 / 1160 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 10, 2008 Page 103 of 1130

REJ09B0402-0200

6.3.4

Interrupt Priority Registers A, D to F, and H to M (IPRA, IPRD to IPRF, and

IPRH to IPRM)

Interrupt priority registers are ten 16-bit readable/writable registers that set priority levels from 0

to 15 for interrupts except NMI. For the correspondence between interrupt request sources and

IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting

a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved

bits that are not assigned should be set H'0 (B'0000).

Bit:

Initial value:

R/W:

987654321

0000000000000000

R/W

IPR[15:12]

IPR[11:8]

IPR[7:4]

IPR[3:0]

Bit

Bit Name

Initial

Value

R/W

Description

15 to 12

IPR[15:12]

0000

R/W

Set priority levels for the corresponding interrupt

source.

0000: Priority level 0 (lowest)

0001: Priority level 1

0010: Priority level 2

0011: Priority level 3

0100: Priority level 4

0101: Priority level 5

0110: Priority level 6

0111: Priority level 7

1000: Priority level 8

1001: Priority level 9

1010: Priority level 10

1011: Priority level 11

1100: Priority level 12

1101: Priority level 13

1110: Priority level 14

1111: Priority level 15 (highest)

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