SH7136 datasheet(133/1160 Pages) RENESAS

133 / 1160 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 10, 2008 Page 107 of 1130

REJ09B0402-0200

IRQCR.IRQn1S

IRQCR.IRQn0S

IRQSR.IRQnF

IRQSR.IRQnL

IRQn pins

RESIRQn

Level

detection

Edge

detection

DTC activation

request

CPU interrupt

request

(Acceptance of IRQn interrupt/

writing 0 after reading IRQnF = 1)

n = 3 to 0

Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control

6.4.2

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral

modules.

Since a different interrupt vector is allocated to each interrupt source, the exception handling

routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can

be allocated to individual on-chip peripheral modules in interrupt priority registers D to F and H to

M (IPRD to IPRF and IPRH to IPRM). On-chip peripheral module interrupt exception handling

sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of

the on-chip peripheral module interrupt that was accepted.

6.4.3

User Break Interrupt

A user break interrupt has a priority level of 15, and occurs when the break condition set in the

user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are

held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3

to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see

section 7, User Break Controller (UBC).

SH7136 Datasheet(PDF) 133 Page - Renesas Technology Corp