SH7136 datasheet(132/1160 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 10, 2008 Page 106 of 1130

REJ09B0402-0200

6.4

Interrupt Sources

6.4.1

External Interrupts

There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules.

Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest).

Giving an interrupt a priority level of 0 masks it.

NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI

interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt

control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception

handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15.

IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Use

the IRQ sense select bits (IRQ31S, IRQ30S to IRQ01S, and IRQ00S) in the IRQ control register

(IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge

detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each

pin using the interrupt priority register A (IPRA).

In the case that the low level detection is selected, an interrupt request signal is sent to the INTC

while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the

IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ

flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR).

In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when

the following change on the IRQ pin is detected: from high to low in falling edge detection mode,

from low to high in rising edge detection mode, and from low to high or from high to low in both

edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the

interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been

detected by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). An IRQ

interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag

after reading 1.

In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register

(SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block

diagram of the IRQ3 to IRQ0 interrupts.

SH7136 Datasheet(PDF) 132 Page - Renesas Technology Corp