SH7136 datasheet(147/1160 Pages) RENESAS

147 / 1160 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 121 of 1130

REJ09B0402-0200

Section 7 User Break Controller (UBC)

The user break controller (UBC) provides functions that simplify program debugging. These

functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug

programs without using an in-circuit emulator. Break conditions that can be set in the UBC are

instruction fetch or data read/write access, data size, data contents, address value, and stop timing

in the case of instruction fetch.

7.1

Features

The UBC has the following features:

1. The following break comparison conditions can be set.

Number of break channels: two channels (channels A and B)

User break can be requested as either the independent or sequential condition on channels A

and B (sequential break setting: channel A and then channel B match with break conditions,

but not in the same bus cycle).

• Address

Comparison bits are maskable in 1-bit units.

One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected.

• Data

32-bit maskable.

One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected.

• Bus cycle

Instruction fetch or data access

• Read/write

• Operand size

Byte, word, and longword

2. A user-designed user-break interrupt exception processing routine can be run.

3. In an instruction fetch cycle, whether a user break is set before or after execution of an

instruction can be selected.

4. Maximum repeat times for the break condition (only for channel B): 2

12 – 1 times.

5. Four pairs of branch source/destination buffers.

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