SH7136 datasheet(150/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 124 of 1130

REJ09B0402-0200

7.3

The user break controller has the following registers. For details on register addresses and register

states during each processing, refer to section 25, List of Registers.

Table 7.2

Abbrevia-

tion

R/W

Initial Value

Address

Access Size

Break address register A

BARA

R/W

H'00000000

H'FFFFF300

Break address mask register A BAMRA

R/W

H'00000000

H'FFFFF304

Break bus cycle register A

BBRA

R/W

H'0000

H'FFFFF308

Break data register A

BDRA

R/W

H'00000000

H'FFFFF310

Break data mask register A

BDMRA

R/W

H'00000000

H'FFFFF314

Break address register B

BARB

R/W

H'00000000

H'FFFFF320

Break address mask register B BAMRB

R/W

H'00000000

H'FFFFF324

Break bus cycle register B

BBRB

R/W

H'0000

H'FFFFF328

Break data register B

BDRB

R/W

H'00000000

H'FFFFF330

Break data mask register B

BDMRB

R/W

H'00000000

H'FFFFF334

Break control register

BRCR

R/W

H'00000000

H'FFFFF3C0

Branch source register

BRSR

H'0xxxxxxx

H'FFFFF3D0

Branch destination register

BRDR

H'0xxxxxxx

H'FFFFF3D4

Execution times break register

BETR

R/W

H'0000

H'FFFFF3DC

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