SH7136 datasheet(153/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 127 of 1130

REJ09B0402-0200

Bit

Bit Name

Initial

Value

R/W

Description

7, 6

CDA[1:0]

R/W

L Bus Cycle/I Bus Cycle Select A

Select the L bus cycle or I bus cycle as the bus cycle of

the channel A break condition.

00: Condition comparison is not performed

01: The break condition is the L bus cycle

10: The break condition is the I bus cycle

11: The break condition is the L bus cycle

5, 4

IDA[1:0]

R/W

Instruction Fetch/Data Access Select A

Select the instruction fetch cycle or data access cycle as

the bus cycle of the channel A break condition.

00: Condition comparison is not performed

01: The break condition is the instruction fetch cycle

10: The break condition is the data access cycle

11: The break condition is the instruction fetch cycle or

data access cycle

3, 2

RWA[1:0]

R/W

Read/Write Select A

Select the read cycle or write cycle as the bus cycle of

the channel A break condition.

00: Condition comparison is not performed

01: The break condition is the read cycle

10: The break condition is the write cycle

11: The break condition is the read cycle or write cycle

1, 0

SZA[1:0]

R/W

Operand Size Select A

Select the operand size of the bus cycle for the channel

A break condition.

00: The break condition does not include operand size

01: The break condition is byte access

10: The break condition is word access

11: The break condition is longword access

Note:

When specifying the operand size, specify the

size which matches the address boundary.

[Legend]

Don't care.

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