SH7136 datasheet(144/1160 Pages) RENESAS

144 / 1160 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 10, 2008 Page 118 of 1130

REJ09B0402-0200

DTC activation

request

DTCECLR

Transfer end

Interrupt request to CPU

Interrupt priority

determination

Interrupt controller

Interrupt source flag clear by DTC

DTCE clear

Interrupt source

flag clear

Interrupt source

DTCER

DTC

Figure 6.6 On-Chip Module Interrupt Control Block Diagram

6.8.1

Handling Interrupt Request Signals as Sources for DTC Activation and CPU

Interrupts

1. For DTC, set the corresponding DTCE bits and DISEL bits to 1.

2. When an interrupt occurs, an activation request is sent to the DTC.

3. When completing a data transfer, the DTC clears the DTCE bit to 0 and sends an interrupt

request to the CPU. The activation source is not cleared.

4. The CPU clears the interrupt source in the interrupt handling routine then checks the transfer

counter value. When the transfer counter value is not 0, the CPU sets the DTCE bit to 1 and

allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary

end processing in the interrupt processing routine.

6.8.2

Handling Interrupt Request Signals as Sources for DTC Activation, but Not CPU

Interrupts

1. For DTC, set the corresponding DTCE bits to 1 and clear the DISEL bits to 0.

2. When an interrupt occurs, an activation request is sent to the DTC.

3. When completing a data transfer, the DTC clears the activation source. No interrupt request is

sent to the CPU because the DTCE bit is held at 1.

4. However, when the transfer counter value = 0, the DTCE bit is cleared to 0 and an interrupt

request is sent to the CPU.

5. The CPU performs the necessary end processing in the interrupt handling routine.

SH7136 Datasheet(PDF) 144 Page - Renesas Technology Corp