SH7136 datasheet(142/1160 Pages) RENESAS

142 / 1160 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 10, 2008 Page 116 of 1130

REJ09B0402-0200

Table 6.4

Interrupt Response Time

Number of Cycles

Item

NMI

IRQ

Peripheral

Modules

Remarks

DTC active judgment



× Bcyc

× Pcyc

Interrupt priority decision

and comparison with mask

bits in SR

× Icyc + 2 ×

Pcyc

× Icyc + 1 ×

Pcyc

× Icyc + 2 ×

Pcyc

Wait for completion of

sequence currently being

executed by CPU

X (

≥ 0)

X (

≥ 0)

X (

≥ 0)

The longest sequence is

for interrupt or address-

error exception handling

(X = 7

× Icyc + m1 + m2

+ m3 + m4). If an

interrupt-masking

instruction follows,

however, the time may

be even longer.

Time from start of interrupt

exception handling until

fetch of first instruction of

exception handling routine

starts

× Icyc +

+ m2 + m3

× Icyc +

+ m2 + m3

× Icyc +

+ m2 + m3

Performs the saving PC

and SR, and vector

address fetch.

Interrupt

response

time

Total:

× Icyc + 2 ×

Pcyc

+ m1 + m2

+ m3 + X

× Icyc + 1 ×

Pcyc

+2 × Bcyc +

+ m2 + m3 +

× Icyc + 3 ×

Pcyc

+ m1 + m2

+ m3 + X

Minimum*:

× Icyc +

× Pcyc

× Icyc +

× Pcyc +

× Bcyc

× Icyc +

× Pcyc

SR, PC, and vector table

are all in on-chip RAM.

Maximum:

× Icyc +

× Pcyc + 2 ×

(m1

+ m2 + m3)

+ m4

× Icyc +

× Pcyc +

× Bcyc + 2 ×

(m1

+ m2 + m3)

+ m4

× Icyc +

× Pcyc + 2 ×

(m1

+ m2 + m3)

+ m4

Notes: *

In the case that m1 = m2 = m3 = m4 = 1

× Icyc.

m1 to m4 are the number of cycles needed for the following memory accesses.

m1: SR save (longword write)

m2: PC save (longword write)

m3: Vector address read (longword read)

m4: Fetch first instruction of interrupt service routine

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