SH7136 datasheet(138/1160 Pages) RENESAS

138 / 1160 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 10, 2008 Page 112 of 1130

REJ09B0402-0200

6.6

Interrupt Operation

6.6.1

Interrupt Sequence

The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the

operations.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest priority interrupt from interrupt requests sent,

according to the priority levels set in interrupt priority registers A, D to F, and H to M (IPRA,

IPRD to IPRF, and IPRH to IPRM). Interrupts that have lower-priority than that of the selected

interrupt are ignored*. If interrupts that have the same priority level or interrupts within a same

module occur simultaneously, the interrupt with the highest priority is selected according to

the default priority shown in table 6.3.

3. The interrupt controller compares the priority level of the selected interrupt request with the

interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the

selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If

the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt

controller accepts the request and sends an interrupt request signal to the CPU.

4. When the interrupt controller accepts an interrupt, a low level is output from the

IRQOUT pin.

5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of

an instruction to be executed. Instead of executing the decoded instruction, the CPU starts

interrupt exception handling.

6. SR and PC are saved onto the stack.

7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR.

8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high

level is output from the

IRQOUT pin. When the accepted interrupt is sensed by edge, a high

level is output from the

IRQOUT pin at the moment when the CPU starts interrupt exception

processing instead of instruction execution as noted in 5. above. However, if the interrupt

controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the

IRQOUT pin holds low level.

9. The CPU reads the start address of the exception handling routine from the exception vector

table for the accepted interrupt, branches to that address, and starts executing the program.

This branch is not a delayed branch.

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