SH7136 datasheet(178/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 152 of 1130

REJ09B0402-0200

Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

Address:

H'00008010, Address mask: H'00000006

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed

or before an instruction with addresses H'00008010 to H'00008016 are executed.

Break Condition Specified for L Bus Data Access Cycle:

(Example 2-1)

• Register specifications

BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BDRA = H'12345678,

BDMRA = H'FFFFFFFF, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A,

BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080

Specified conditions: Channel A/channel B independent mode

Address:

H'00123456, Address mask: H'00000000

Data:

H'12345678, Data mask: H'FFFFFFFF

Bus cycle: L bus/data access/read (operand size is not included in the condition)

Address:

H'000ABCDE, Address mask: H'000000FF

Data:

H'0000A512, Data mask: H'00000000

Bus cycle: L bus/data access/write/word

On channel A, a user break occurs with longword read from address H'00123454, word read

from address H'00123456, or byte read from address H'00123456. On channel B, a user break

occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.

SH7136 Datasheet(PDF) 178 Page - Renesas Technology Corp