SH7136 datasheet(176/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 150 of 1130

REJ09B0402-0200

Address:

H'0003722E, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

After an instruction with address H'00037226 is executed, a user break occurs before an

instruction with address H'0003722E is executed.

(Example 1-3)

• Register specifications

BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000,

BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054,

BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000

Specified conditions: Channel A/channel B independent mode

Address:

H'00027128, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/write/word

Address:

H'00031415, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B,

no user break occurs since instruction fetch is performed for an even address.

(Example 1-4)

• Register specifications

BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000,

BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056,

BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008

Specified conditions: Channel A/channel B sequential mode

Address:

H'00037226, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/write/word

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